Motorola MPC8260 - Manual (Page 609)

MOTOROLA Chapter 21. SCC HDLC Mode 21-1
Chapter 21
SCC HDLC Mode
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210
High-level data link control (HDLC) is one of the most common protocols in the data link
layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC,
SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in
particular. Figure 21-1 shows the HDLC framing structure.
HDLC uses a zero insertion/deletion process (bit-stufÞng) to ensure that a data bit pattern
matching the delimiter ßag does not occur in a Þeld between ßags. The HDLC frame is
synchronous and relies on the physical layer for clocking and synchronization of the
transmitter/receiver.
An address Þeld is needed to carry the frame's destination address because the layer 2 frame
can be sent over point-to-point links, broadcast networks, packet-switched or circuit-
switched systems. An address Þeld is commonly 0, 8, or 16 bits, depending on the data link
layer protocol. SDLC and LAPB use an 8-bit address. SS#7 has no address Þeld because it
is always used in point-to-point signaling links. LAPD divides its 16-bit address into
different Þelds to specify various access points within one device. LAPD also deÞnes a
broadcast address. Some HDLC-type protocols permit addressing beyond 16 bits.
The 8- or 16-bit control Þeld provides a ßow control number and deÞnes the frame type
(control or data). The exact use and structure of this Þeld depends on the protocol using the
frame. The length of the data in the data Þeld depends on the frame protocol. Layer 3 frames
are carried in this data Þeld. Error control is implemented by appending a cyclic redundancy
check (CRC) to the frame, which in most protocols is 16 bits long but can be as long as 32
bits. In HDLC, the lsb of each octet is sent Þrst; the msb of the CRC is sent Þrst.
HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. In a
nonmultiplexed modem interface, SCC outputs connect directly to external pins. Modem
signals can be supported through port C. The Rx and Tx clocks can be supplied from either
the bank of baud rate generators, by the DPLL, or externally. An SCC can also be connected
through the TDM channels of the serial interface (SI). In HDLC mode, an SCC becomes
an HDLC controller, and consists of separate transmit and receive sections whose
operations are asynchronous with the core and can either be synchronous or asynchronous
with respect to other SCCs.