Motorola MPC8260 - Manual (Page 197)

MOTOROLA Part III. The Hardware Interface Part III-i
Part III
The Hardware Interface
Intended Audience
Part III is intended for system designers who need to understand how each MPC8260 signal
works and how those signals interact.
Contents
Part III describes external signals, clocking, memory control, and power management of
the MPC8260.
It contains the following chapters:
¥ Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and
describes the MPC8260 signals.
¥ Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus.
¥ Chapter 8, ÒThe 60x Bus,Ó describes the operation of the bus used by PowerPC
processors.
¥ Chapter 9, ÒClocks and Power Control,Ó describes the clocking architecture of the
MPC8260.
¥ Chapter 10, ÒMemory Controller,Ó describes the memory controller, which
controlling a maximum of eight memory banks shared between a general-purpose
chip-select machine (GPCM) and three user-programmable machines (UPMs).
¥ Chapter 11, ÒSecondary (L2) Cache Support,Ó provides information about
implementation and conÞguration of a level-2 cache.
¥ Chapter 12, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-accessible
test access port (TAP), which is fully compatible with the IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.