Motorola MPC8260 - Manual (Page 919)

MOTOROLA Chapter 31. FCC HDLC Controller 31-17
Part IV. Communications Processor Module
Table 31-10 describes FCCS bits.
Table 31-10. FCCS Register Field Descriptions
Bits Name Description
0Р4 С Reserved, should be cleared.
5 FG Flags. While FG is cleared, each time a new bit is received the most recently received 8 bits are
examined to see if a ßag is present. FG is set as soon as an HDLC ßag (0x7E) is received on the line.
Once FG is set, it remains set at least 8 bit times while the next 8 bits of input data are examined. If
another ßag occurs, FG stays set for at least another eight bits. Otherwise, FG is cleared and the
search begins again.
0 HDLC ßags are not currently being received.
1 HDLC ßags are currently being received.
6 Ñ Reserved, should be cleared.
7 ID Idle status. ID is set when the RXD signal is a logic one for 15 or more consecutive bit times; it is
cleared after a logic zero is received.
0 The line is busy.
1 The line is idle.