Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 112)

Mentor VIP AE AXI3/4 User Guide, V10.2b 94
SystemVerilog AXI3 and AXI4 Slave BFMs
get_write_addr_cycle()
September 2013
get_write_addr_cycle()
This blocking AXI4 task waits until the write address channel AWVALID signal is asserted.
AXI3 BFM
Note
The get_write_addr_cycle() task is not available in the AXI3 BFM.
AXI4 Example
// Wait for a single write address cycle
bfm.get_write_addr_cycle();
Prototype task automatic get_write_addr_cycle();
Arguments None
Returns None