Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 69)

SystemVerilog AXI3 and AXI4 Master BFMs
execute_write_addr_phase()
Mentor VIP AE AXI3/4 User Guide, V10.2b 51
September 2013
execute_write_addr_phase()
This task executes a master write address phase previously created by the
create_write_transaction() function. This phase can be blocking (default) or nonblocking,
defined by the transaction operation_mode field.
It sets the AWVALID protocol signal at the appropriate time defined by the transaction
address_valid_delay field.
AXI3 Example
// Declare a local variable to hold the transaction record.
axi_transaction write_trans;
// Create a write transaction with start address of 0 and assign
// it to the local write_trans variable.
write_trans = bfm.create_write_transaction(0);
....
// Execute the write_trans transaction.
bfm.execute_transaction(write_trans);
AXI4 Example
// Declare a local variable to hold the transaction record.
axi4_transaction write_trans;
// Create a write transaction with start address of 0 and assign
// it to the local write_trans variable.
write_trans = bfm.create_write_transaction(0);
....
// Execute the write_trans transaction.
bfm.execute_transaction(write_trans);
Prototype // * = axi | axi4
task automatic execute_write_addr_phase
(
*_transaction trans
);
Arguments trans The *_transaction record.
Returns None