Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 23)

Mentor VIP AE AXI3/4 User Guide, V10.2b 5
September 2013
Chapter 1
Mentor VIP Altera Edition
The Mentor ® Verification IP (VIP) Altera ® Edition (AE) provides bus functional models
(BFMs) to simulate the behavior and to facilitate IP verification. The Mentor VIP AE includes
the following interfaces:
•
AXI3 TM BFM with master, slave, and inline monitor interfaces
•
AXI4 TM BFM with master, slave, and inline monitor interfaces
Advantages of Using BFMs and Monitors
Using the Mentor VIP AE has the following advantages:
•
Accelerates the verification process by providing key verification testbench
components.
•
Provides BFM components that implement the AMBA AXI Protocol Specification,
which serves as a reference for the protocol.
•
Provides a full suite of configurable assertion checking in each BFM.
Implementation of BFMs
The Mentor VIP AE BFMs, master, slave, and inline monitor components are implemented in
SystemVerilog. Also included are wrapper components so that the BFMs can be used in VHDL
verification environments with simulators that support mixed-language simulation.
The Mentor VIP AE provides a set of APIs for each BFM that you can use to construct,
instantiate, control, and query signals in all BFM components. Your test programs must use
only these public access methods and events to communicate with each BFM. To ensure
support in current and future releases, your test programs must use the standard set of APIs to
interface with the BFMs. Nonstandard APIs and user-generated interfaces can not be supported
in future releases.
The test program drives the stimulus to the DUTs and determines whether the behavior of the
DUTs is correct by analyzing the responses. The BFMs translate the test program stimuli
(transactions), creating the signaling for the AMBA AXI Protocol Specification. The BFMs also
check for protocol compliance by firing an assertion when a protocol error is observed.