Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 730)

Mentor VIP AE AXI3/4 User Guide, V10.2b 710
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
September 2013
// Enum type for master ready delay mode
// AXI4_VALID2READY - Ready delay for a phase will be applied from
// start of phase (Means from when VALID is asserted).
// AXI4_TRANS2READY - Ready delay will be applied from the end of
// previous phase. This might result in ready before
// valid.
typedef enum bit
{
AXI4_VALID2READY = 1'b0,
AXI4_TRANS2READY = 1'b1
} axi4_master_ready_delay_mode_e;
/////////////////////////////////////////////////
// Code user could edit according to requirements
/////////////////////////////////////////////////
// Variable : m_wr_resp_phase_ready_delay
int m_wr_resp_phase_ready_delay = 2;
// Variable : m_rd_data_phase_ready_delay
int m_rd_data_phase_ready_delay = 2;
// Master ready delay mode seclection : default it is VALID2READY
axi4_master_ready_delay_mode_e master_ready_delay_mode =
AXI4_VALID2READY;
initial
begin
axi4_transaction trans, trans1, trans2, trans3, trans4, trans5,
trans6, trans7, trans8;
/*******************
** Initialization **
*******************/
bfm.wait_on(AXI4_RESET_0_TO_1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
/*******************
** **
*******************/
fork
handle_write_resp_ready;
handle_read_data_ready;
join_none
/************************
** Traffic generation: **
************************/
// 4 x Writes
// Write data value 1 on byte lanes 1 to address 1.
trans = bfm.create_write_transaction(1);
trans.set_data_words(32'h0000_0100, 0);
trans.set_write_strobes(4'b0010, 0);
$display ( "@ %t, master_test_program: Writing data (1) to address
(1)", $time);