Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 660)

Mentor VIP AE AXI3/4 User Guide, V10.2b 640
VHDL Tutorials
Verifying a Master DUT
September 2013
m_rd_addr_phase_ready_delay
The m_rd_addr_phase_ready_delay variable holds the ARREADY signal delay. The delay value
extends the length of the read address phase by a number of ACLK cycles. The starting point of
the delay is determined by the assertion of the ARVALID signal.
Example 11-32 shows the ARREADY signal delayed by 2 ACLK cycles. You can edit this
variable to change the ARREADY signal delay.
Example 11-32. m_rd_addr_phase_ready_delay
-- Variable : m_rd_addr_phase_ready_delay
signal m_rd_addr_phase_ready_delay : integer := 2;
m_wr_data_phase_ready_delay
The m_wr_data_phase_ready_delay variable holds the WREADY signal delay. The delay value
extends the length of each write data phase (beat) in a write data burst by a number of ACLK
cycles. The starting point of the delay is determined by the assertion of the WVALID signal.
Example 11-33 shows the WREADY signal delayed by 2 ACLK cycles. You can edit this
function to change the WREADY signal delay.
Example 11-33. m_wr_data_phase_ready_delay
-- Variable : m_wr_data_phase_ready_delay
signal m_wr_data_phase_ready_delay : integer := 2;
set_wr_resp_valid_delay()
The set_wr_resp_valid_delay() procedure has two prototypes (path_id is optional), and
configures the BVALID signal to be delayed by a number of ACLK cycles with the effect of
delaying the start of the write response phase. The delay value of the BVALID signal is stored in
the write_response_valid_delay transaction field.
Example 11-34 shows the BVALID signal delay set to 2 ACLK cycles. You can edit this function
to change the BVALID signal delay.
Example 11-34. set_wr_resp_valid_delay()
-- Procedure : set_wr_resp_valid_delay
-- This is used to set write response phase valid delay to start driving
-- write response phase after specified delay.
procedure set_wr_resp_valid_delay(id : integer; path_id : in axi4_path_t;
signal tr_if : inout axi4_vhd_if_struct_t) is
begin
set_write_response_valid_delay(2, id, index, path_id, tr_if);
end set_wr_resp_valid_delay;