Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 761)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI3 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 741
September 2013
variable read_trans: integer;
begin
set_config(AXI_CONFIG_MAX_OUTSTANDING_RD,
m_max_outstanding_read_trans, index, AXI_PATH_3, axi_tr_if_3(index));
set_config(AXI_CONFIG_MAX_OUTSTANDING_WR,
m_max_outstanding_write_trans, index, AXI_PATH_3, axi_tr_if_3(index));
wait_on(AXI_RESET_0_TO_1, index, AXI_PATH_3, axi_tr_if_3(index));
wait_on(AXI_CLOCK_POSEDGE, index, AXI_PATH_3, axi_tr_if_3(index));
loop
create_slave_transaction(read_trans, index, AXI_PATH_3,
axi_tr_if_3(index));
set_read_address_ready_delay(read_trans, AXI_PATH_3,
axi_tr_if_3(index));
get_read_addr_phase(read_trans, index, AXI_PATH_3,
axi_tr_if_3(index));
push_transaction_id(read_trans, AXI_QUEUE_ID_1, index, AXI_PATH_3,
axi_tr_if_3(index));
end loop;
wait;
end process;
-- handle_read : read data and response through path 4
-- This process reads data from memory and send read data/response
either at
-- burst or phase level depending upon slave working mode.
process
variable read_trans: integer;
variable burst_length : integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
loop
pop_transaction_id(read_trans, AXI_QUEUE_ID_1, index, AXI_PATH_4,
axi_tr_if_4(index));
set_read_data_valid_delay(read_trans, AXI_PATH_4,
axi_tr_if_4(index));
get_burst_length(burst_length, read_trans, index, AXI_PATH_4,
axi_tr_if_4(index));
for i in 0 to burst_length loop
get_read_addr(read_trans, i, 0, byte_length, addr, index,
AXI_PATH_4, axi_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, i, 0, byte_length, addr, data, index,
AXI_PATH_4, axi_tr_if_4(index));
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_read_addr(read_trans, i, j, byte_length, addr, index,
AXI_PATH_4, axi_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, i, j, byte_length, addr, data,
index, AXI_PATH_4, axi_tr_if_4(index));
end loop;
end if;
if slave_mode = AXI_PHASE_SLAVE then
execute_read_data_phase(read_trans, i, index, AXI_PATH_4,
axi_tr_if_4(index));