Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 190)

Mentor VIP AE AXI3/4 User Guide, V10.2b 172
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
Figure 6-6. slave_ready_delay_mode = AXI4_VALID2READY
The nondefault configuration (slave_ready_delay_mode = AXI4_TRANS2READY) corresponds
to the delay measured from the completion of a previous transaction phase (*VALID and
*READY both asserted).
Figure 6-7 shows how to achieve a *READY before *VALID
handshake.
Figure 6-7. slave_ready_delay_mode = AXI4_TRANS2READY
*VALID
*READY
ACLK
*_valid_delay = 4 *_ready_delay = 2
*VALID
*READY
ACLK
*_valid_delay = 4
*_ready_delay = 2