Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 715)

Mentor VIP AE AXI3/4 User Guide, V10.2b 695
September 2013
Appendix B
SystemVerilog AXI3 and AXI4 Test
Programs
SystemVerilog AXI3 Master BFM Test Program
The following code example contains a simple AXI3 master test program that shows the master
BFM API being used to communicate with a slave and create stimulus. This test program is
discussed further in the
SystemVerilog Tutorials chapter.
// **********************************************************************
//
// Copyright 2007-2013 Mentor Graphics Corporation
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
// THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
// TERMS.
//
// **********************************************************************
/*
This is a simple example of an AXI master to demonstrate the
mgc_axi_master BFM usage.
This master performs a directed test, initiating 4 sequential writes,
followed by 4 sequential reads. It then verifies that the data read out
matches the data written.
For the sake of simplicity, only one data cycle is used (default AXI
burst length encoding 0).
It then initiates two write data bursts followed by two read data
bursts.
It then initiates 4 outstanding writes, followed by 4 reads. It then
verifies that the data read out matches the data written.
*/
import mgc_axi_pkg::*;
module master_test_program #(int AXI_ADDRESS_WIDTH = 32, int
AXI_RDATA_WIDTH = 1024, int AXI_WDATA_WIDTH = 1024, int AXI_ID_WIDTH = 18)
(
mgc_axi_master bfm
);
initial
begin
axi_transaction trans, trans1, trans2, trans3, trans4, trans5, trans6,
trans7, trans8;