Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 199)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 181
September 2013
handle_write()
The handle_write() task works in a similar way as that previously described for the
handle_read() task. The main difference is that the write transaction handling gets the write data
burst and stores it in the slave test program Internal Memory depending on the slave_mode
setting, and adhering to the state of the WSTRB write strobes signal. There is an additional write
response phase that is required for the write response channel, as shown in
Example 6-46 below.
Example 6-46. handle_write()
// Task : handle_write
// This method receive write data burst or phases for write
// transaction depending upon slave working mode, write data to
// memory and then send response
task automatic handle_write(input axi4_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
if (slave_mode == AXI4_TRANSACTION_SLAVE)
begin
bfm.get_write_data_burst(write_trans);
for( int i = 0; bfm.get_write_addr_data(write_trans,
i, addr, data); i++ )
begin
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
else
begin
for(int i = 0; (last == 1'b0); i++)
begin
bfm.get_write_data_phase(write_trans, i, last);
void'(bfm.get_write_addr_data(write_trans, i, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
set_wr_resp_valid_delay(write_trans);
bfm.execute_write_response_phase(write_trans);
endtask
handle_write_addr_ready()
The handle_write_addr_ready() task handles the AWREADY signal for the write address
channel. In a forever loop it delays the assertion of the AWREADY signal based on the settings
of the
slave_ready_delay_mode and m_wr_resp_phase_ready_delay as shown in Example
below.
If the slave_delay_ready_mode = AXI4_VALID2READY then the AWREADY signal is
deasserted using the nonblocking call to the
execute_write_data_ready() task and waits for a