Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 203)

Mentor VIP AE AXI3/4 User Guide, V10.2b 185
September 2013
Chapter 7
VHDL API Overview
This section describes the VHDL Application Programming Interface (API) procedures for all
the BFM (master, slave, and monitor) components. For each BFM, you can configure protocol
transaction fields that execute on the protocol signals and control the operational transaction
fields that permit delays between the handshake signals for each of the five address, data, and
response channels.
In addition, each BFM API has procedures that wait for certain events to occur on the system
clock and reset signals, and procedures to get and set information about a particular transaction.
Note
The VHDL API is built on the SystemVerilog API. An internal VHDL to SystemVerilog
(SV) wrapper casts the VHDL BFM API procedure calls to the SystemVerilog BFM API
tasks and functions.