Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 634)

Mentor VIP AE AXI3/4 User Guide, V10.2b 614
VHDL Tutorials
Verifying a Slave DUT
September 2013
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Variables m_wr_resp_phase_ready_delay and m_rd_data_phase_ready_delay to set the
delay of the BREADY and RREADY signals
The following sections described the main processes and variables:
m_wr_resp_phase_ready_delay
The m_wr_resp_phase_ready_delay variable holds the BREADY signal delay. The delay value
extends the length of the write response phase by a number of ACLK cycles.
Example 11-7 below shows the AWREADY signal delayed by 2 ACLK cycles. You can edit this
variable to change the AWREADY signal delay.
Example 11-7. m_wr_resp_phase_ready_delay
-- Variable : m_wr_resp_phase_ready_delay
signal m_wr_resp_phase_ready_delay :integer := 2;
m_rd_data_phase_ready_delay
The m_rd_data_phase_ready_delay variable holds the RREADY signal delay. The delay value
extends the length of each read data phase (beat) in a read data burst by a number of ACLK
cycles.
Example 11-8 below shows the RREADY signal delayed by 2 ACLK cycles. You can edit this
variable to change the RREADY signal delay.