Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 727)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI3 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 707
September 2013
// Task : process_write
// This method keep receiving write address phase
// and calls another method to
// process received transaction.
task process_write;
forever
begin
axi_transaction write_trans;
write_trans = bfm.create_slave_transaction();
set_write_address_ready_delay(write_trans);
bfm.get_write_addr_phase(write_trans);
fork
begin
automatic axi_transaction t = write_trans;
handle_write(t);
end
join_none
#0;
end
endtask
// Task : handle_write
// This method receive write data burst or phases for write transaction
// depending upon slave working mode, write data to memory and then send
// response
task automatic handle_write(input axi_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
set_write_data_ready_delay(write_trans);
if (slave_mode == AXI_TRANSACTION_SLAVE)
begin
bfm.get_write_data_burst(write_trans);
for( int i = 0; bfm.get_write_addr_data(write_trans, i, addr, data);
i++ )
begin
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
else
begin
for(int i = 0; (last == 1'b0); i++)
begin
bfm.get_write_data_phase(write_trans, i, last);
void'(bfm.get_write_addr_data(write_trans, i, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end