Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 747)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 727
September 2013
// Task : handle_read_addr_ready
// This method assert/de-assert the read address channel ready signal.
// Assertion and de-assertion is done based on following
// variable's value:
// m_rd_addr_phase_ready_delay
// slave_ready_delay_mode
task automatic handle_read_addr_ready;
bit seen_valid_ready;
int tmp_ready_delay;
int tmp_config_num_outstanding_rd_phase;
axi4_slave_ready_delay_mode_e tmp_mode;
forever
begin
tmp_config_num_outstanding_rd_phase =
bfm.get_config(AXI4_CONFIG_NUM_OUTSTANDING_RD_PHASE);
while ((tmp_config_num_outstanding_rd_phase >=
m_max_outstanding_read_trans) && (m_max_outstanding_read_trans > 0))
begin
bfm.wait_on(AXI4_CLOCK_POSEDGE);
tmp_config_num_outstanding_rd_phase =
bfm.get_config(AXI4_CONFIG_NUM_OUTSTANDING_RD_PHASE);
end
wait(m_rd_addr_phase_ready_delay > 0);
tmp_ready_delay = m_rd_addr_phase_ready_delay;
tmp_mode = slave_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_read_addr_ready(1'b0);
join_none
bfm.get_read_addr_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_read_addr_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.ARVALID === 1'b1) && (bfm.ARREADY === 1'b1)));
end
fork
bfm.execute_read_addr_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);