Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 763)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 743
September 2013
VHDL AXI4 Master BFM Test Program
The following code example contains a simple AXI4 master test program that shows the master
BFM API being used to communicate with a slave and to create stimulus. This test program is
discussed further in the
VHDL Tutorials chapter.
-- **********************************************************************
--
-- Copyright 2007-2011 Mentor Graphics Corporation
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
TERMS.
--
-- **********************************************************************
-- This is a simple example of an AXI master to demonstrate the
mgc_axi_master BFM usage.
--
-- This master performs a directed test, initiating 4 sequential
writes, followed by 4 sequential reads.
-- It then verifies that the data read out matches the data written.
-- For the sake of simplicity, only one data cycle is used (default AXI
burst length encoding 0).
--
-- It then initiates two write data bursts followed by two read data
bursts.
library ieee ;
use ieee.std_logic_1164.all;
library work;
use work.all;
use work.mgc_axi_bfm_pkg.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity master_test_program is
generic (AXI_ADDRESS_WIDTH : integer := 32;
AXI_RDATA_WIDTH : integer := 1024;
AXI_WDATA_WIDTH : integer := 1024;
AXI_ID_WIDTH : integer := 18;
index : integer range 0 to 511 :=0
);
end master_test_program;
architecture master_test_program_a of master_test_program is
begin
-- Master test
process
variable tr_id: integer;