Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 191)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 173
September 2013
Example 6-40 shows the configuration of the slave_ready_delay_mode to its default value.
Example 6-40. slave_ready_delay_mode
// Enum type for slave ready delay mode
// AXI4_VALID2READY - Ready delay for a phase will be applied from
// start of phase (Means from when VALID is asserted).
// AXI4_TRANS2READY - Ready delay will be applied from the end of
// previous phase. This might result in ready before
valid.
typedef enum bit
{
AXI4_VALID2READY = 1'b0,
AXI4_TRANS2READY = 1'b1
} axi4_slave_ready_delay_mode_e;
// Slave ready delay mode seclection : default it is AXI4_VALID2READY
axi4_slave_ready_delay_mode_e slave_ready_delay_mode = AXI4_VALID2READY;
slave_mode
There is a slave_mode transaction field that you configure to control the behavior of reading and
writing to
Internal Memory . It has two modes AXI4_TRANSACTION_SLAVE and
AXI4_PHASE_SLAVE.
Example 6-41. slave_mode
// Enum type for slave mode
// AXI4_TRANSACTION_SLAVE - Works at burst level (write data is received
// at burst and read data/response is sent in burst)
// AXI4_PHASE_SLAVE - Write data and read data/response is serviced
// at phase level
typedef enum bit
{
AXI4_TRANSACTION_SLAVE = 1'b0,
AXI4_PHASE_SLAVE = 1'b1
} axi4_slave_mode_e;
// Slave mode selection : Default is transaction-level slave
axi4_slave_mode_e slave_mode = AXI4_TRANSACTION_SLAVE;
The default AXI4_TRANSACTION_SLAVE mode “saves up” an entire data burst and modifies
the slave test program
Internal Memory in zero time for the whole burst. Therefore, a burst read
from Internal Memory is buffered from the beginning of the burst to the end of the burst. The
buffered read burst data is then transmitted over the protocol signals to the master on a phase-
by-phase (beat-by-beat) basis. For a write, the data burst received over the protocol signals is
buffered from the beginning of the burst to the end of the burst. At the end of the write burst, the
buffered contents are written to the Internal Memory.
The AXI4_PHASE_SLAVE mode updates the slave test program Internal Memory on each data
phase (beat). Therefore, a read from the Internal Memory occurs only when the read data phase
(beat) actually starts to be transmitted on the protocol signals. For a write, data is written to the
Internal Memory as soon as each write data phase (beat) is received on the protocol signals.