Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 723)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI3 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 703
September 2013
SystemVerilog AXI3 Slave BFM Test Program
The following code example contains a simple AXI3 slave test program that shows the slave
BFM API being used to communicate with a master and create stimulus. This test program is
discussed further in the
SystemVerilog Tutorials chapter.
// ********************************************************************
//
// Copyright 2007-2013 Mentor Graphics Corporation
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
// THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
// TERMS.
//
// **********************************************************************
/*
This is a simple example of an AXI Slave to demonstrate the
mgc_axi_slave BFM usage.
This is a fairly generic slave which handles almost all write and read
transaction
scenarios from master. It handles write data with address as well as
data after address
both. It handles outstanding read and write transactions.
This slave code is divided in two parts, one which user might need to
edit to change slave
mode (Transaction/burst or Phase level) and memory handling.
Out of the code which is grouped as user do not need to edit, could be
edited for achieving
required phase valid/ready delays.
*/
import mgc_axi_pkg::*;
module slave_test_program #(int AXI_ADDRESS_WIDTH = 32, int
AXI_RDATA_WIDTH = 32, int AXI_WDATA_WIDTH = 32, int AXI_ID_WIDTH = 18)
(
mgc_axi_slave bfm
);
typedef bit [((AXI_ADDRESS_WIDTH) - 1) : 0] addr_t;