Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 756)

Mentor VIP AE AXI3/4 User Guide, V10.2b 736
VHDL AXI3 and AXI4 Test Programs
VHDL AXI3 Master BFM Test Program
September 2013
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
TERMS.
--
--
*************************************************************************
****
--
-- This is a simple example of an AXI Slave to demonstrate the
mgc_axi_slave BFM usage.
--
-- This is a fairly generic slave which handles almost all write and read
transaction
-- scenarios from master. It handles write data with address as well as
data after address
-- both. It handles outstanding read and write transactions.
--
-- This slave code is divided in two parts, one which user might need to
edit to change slave
-- mode (Transaction/burst or Phase level) and memory handling.
-- Out of the code which is grouped as user do not need to edit, could be
edited for achieving
-- required phase valid/ready delays.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.all;
use work.mgc_axi_bfm_pkg.all;
entity slave_test_program is
generic (AXI_ADDRESS_WIDTH : integer := 32;
AXI_RDATA_WIDTH : integer := 1024;
AXI_WDATA_WIDTH : integer := 1024;
AXI_ID_WIDTH : integer := 18;
index : integer range 0 to 511 := 0
);
end slave_test_program;
architecture slave_test_program_a of slave_test_program is
type axi_slave_mode_e is (AXI_TRANSACTION_SLAVE, AXI_PHASE_SLAVE);
type memory_t is array (0 to 2**16-1) of std_logic_vector(7 downto 0);
shared variable mem : memory_t;
signal slave_mode : axi_slave_mode_e := AXI_TRANSACTION_SLAVE;
signal m_max_outstanding_read_trans : integer := 2;
signal m_max_outstanding_write_trans : integer := 2;
procedure do_byte_read(addr : in std_logic_vector(AXI_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0));
procedure do_byte_write(addr : in std_logic_vector(AXI_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0));
procedure set_write_address_ready_delay(id : integer; signal tr_if :
inout axi_vhd_if_struct_t);