Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 43)

SystemVerilog API Overview
Operational Transaction Fields
Mentor VIP AE AXI3/4 User Guide, V10.2b 25
September 2013
Note
The above test program code segments are for AXI3 BFMs. For AXI4 BFMs, substitute
the axi_transaction type definition with axi4_transaction and axi_prot_e with
axi4_prot_e.
Operational Transaction Fields
Operational transaction fields control the way a transaction is executed onto the protocol
signals. They also indicate when a data phase (beat) or transaction is complete.
Automatic Generation of Byte Lane Strobes
The master BFM permits unaligned and narrow write transfers by using byte lane strobe
(WSTRB) signals to indicate which byte lanes contain valid data per data phase (beat).
When you create a write transaction in your master BFM test program, the write_strobes
variable is available to store the write strobe values for each write data phase (beat) in the
transaction. To assist you in creating the correct byte lane strobes, automatic correction of any
previously set write_strobes is performed by default during execution of the write transaction,
or write data phase (beat). You can disable this default behavior by setting the operational
transaction field gen_write_strobes = 0, which allows any previously set write_strobes to pass
through uncorrected onto the protocol WSTRB signals. In this mode, with the automatic
correction disabled, you are responsible for setting the correct write_strobes for the whole
transaction.
The automatic correction algorithm performs a bit-wise AND operation on any previously set
write_strobes. To do the corrections, the correction algorithm uses the equations described in
the AMBA AXI Protocol Specification, section A3.4.1 that define valid write data byte lanes
for legal protocol. Therefore, if you require automatic generation of all write_strobes, before the
write transaction executes, you must set all write_strobes to 1, indicating that all bytes lanes
initially contain valid write data prior to the execution of the write transaction. Automatic
correction then sets the relevant write_strobes to 0 to produce legal protocol WSTRB signals.
For example, Figure 2-2 below shows byte lanes that can contain valid data for a write
transaction with a starting address = 0x01, size = 0b001 (2 bytes), type = INCR, and the length
= 0b0010 (3 beats) for a 32-bit write data bus.