Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 180)

Mentor VIP AE AXI3/4 User Guide, V10.2b 162
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
Similarly, a read transaction that starts before a previous read transaction has completed can be
pipelined.
Figure 6-5 shows the read channel having two concurrent read_trans transactions,
whereby the read_addr_phase[1] and read_data_burst[0] are concurrently active on the read
address and data channels, respectively.
Figure 6-5. Slave Test Program Advanced API Tasks
In an initial block, the slave test program configures the maximum number of outstanding read
and write transactions before waiting for the ARESETn signal to be deactivated. The following
positive edge of ACLK starts the processing of any read or write transactions simultaneously in
a fork-join block, as demonstrated in
Example 6-26 .