Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 189)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 171
September 2013
Example 6-38 shows the RVALID signal delay incrementing by an ACLK cycle between each
read data phase for the length of the burst. You can edit this function to change the RVALID
signal delay.
Example 6-38. set_read_data_valid_delay()
// Function : set_read_data_valid_delay
// This is used to set read response phase valid delays to start
// driving read data/response phases after specified delay.
function void set_read_data_valid_delay(axi4_transaction trans);
for (int i = 0; i < trans.data_valid_delay.size(); i++)
trans.set_data_valid_delay(i, i);
endfunction
set_wr_resp_valid_delay()
The set_wr_resp_valid_delay() function, when called, configures the BVALID signal to be
delayed by a number of ACLK cycles with the effect of delaying the start of the write response
phase. The delay value of the BVALID signal is stored in the write_response_valid_delay
transaction field.
Example 6-39 shows the BVALID signal delay set to 2 ACLK cycles. You can edit this function
to change the BVALID signal delay.
Example 6-39. set_wr_resp_valid_delay()
// Function : set_wr_resp_valid_delay
// This is used to set write response phase valid delay to start
// driving write response phase after specified delay.
function void set_wr_resp_valid_delay(axi4_transaction trans);
trans.set_write_response_valid_delay(2);
endfunction
slave_ready_delay_mode
The slave_ready_delay_mode variable holds the configuration that defines the starting point of
any delay applied to the *READY signals. It can be configured to the enumerated type values of
AXI4_VALID2READY (default) or AXI4_TRANS2READY.
The default configuration (slave_ready_delay_mode = AXI4_VALID2READY) corresponds to
the delay measured from the positive edge of ACLK when *VALID is asserted.
Figure 6-6 shows
how to achieve a *VALID before *READY handshake.