Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 652)

Mentor VIP AE AXI3/4 User Guide, V10.2b 632
VHDL Tutorials
Verifying a Master DUT
September 2013
Example 11-25. process write
-- process_write : write address phase through path 0
-- This process keep receiving write address phases and pushes
-- the transaction into a queue via the push_transaction_id procedure.
process
variable write_trans : integer;
begin
set_config
(
AXI_CONFIG_MAX_OUTSTANDING_WR, m_max_outstanding_write_trans,
index, axi_tr_if_0(index)
);
wait_on(AXI_RESET_0_TO_1, index, axi_tr_if_0(index));
wait_on(AXI_CLOCK_POSEDGE, index, axi_tr_if_0(index));
loop
create_slave_transaction(write_trans, index, axi_tr_if_0(index));
set_write_address_ready_delay(write_trans, axi_tr_if_0(index));
get_write_addr_phase(write_trans, index, axi_tr_if_0(index));
push_transaction_id(write_trans, AXI_QUEUE_ID_0, index,
axi_tr_if_0(index));
end loop;
wait;
end process;
The handle_write code extract demonstrates how to write a data burst to an internal memory
using buffered and unbuffered approaches.
To perform pipelining of the AXI3 address and data phases of one transaction concurrently with
another transaction, the Advanced Slave API provides procedures with an optional path_id
argument. This permits multiple threads of code execution in the Slave API. The following
handle_write code uses path_id = AXI_PATH_1, as an example.
Initially, a number of local variables are defined to hold the transaction index write_trans and
some of the transaction fields, such as burst length, data, etc. In a loop, the existing record of the
write_trans transaction is popped from the queue identifier AXI_QUEUE_ID_0 via the
pop_transaction_id procedure. The delay for the WREADY signal is then set by the
set_write_data_ready_delay procedure.
If the slave_mode is configured to AXI_TRANSACTION_SLAVE (buffered) the code waits for a
complete write data burst by the get_write_data_burst procedure before continuing. The burst
length of the write data burst is obtained using the get_burst_length procedure. The resulting
burst_length is then used to set the subsequent maximum inner loop i count for the number of
data beats in the burst. Loop i gets the address and data pairs from the transaction via the
get_write_addr_data procedure before calling the do_byte_write procedure which writes the
data byte into the memory mem at the corresponding addr address. If the number of bytes to be
written (for this beat) is more than one, then loop j writes the remaining bytes of this beat into
the memory mem. Loop i then repeats for each data beat up to the length of the data burst.