Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 745)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 725
September 2013
// Task : handle_write
// This method receive write data burst or phases for write transaction
// depending upon slave working mode, write data to memory and then send
// response
task automatic handle_write(input axi4_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
if (slave_mode == AXI4_TRANSACTION_SLAVE)
begin
bfm.get_write_data_burst(write_trans);
for( int i = 0; bfm.get_write_addr_data(write_trans, i, addr, data);
i++ )
begin
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
else
begin
for(int i = 0; (last == 1'b0); i++)
begin
bfm.get_write_data_phase(write_trans, i, last);
void'(bfm.get_write_addr_data(write_trans, i, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
set_wr_resp_valid_delay(write_trans);
bfm.execute_write_response_phase(write_trans);
endtask
// Task : handle_write_addr_ready
// This method assert/de-assert the write address channel ready signal.
// Assertion and de-assertion is done based on
m_wr_addr_phase_ready_delay
task automatic handle_write_addr_ready;
bit seen_valid_ready;
int tmp_ready_delay;
int tmp_config_num_outstanding_wr_phase;
axi4_slave_ready_delay_mode_e tmp_mode;