Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 771)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 751
September 2013
variable write_trans : integer;
begin
set_config(AXI4_CONFIG_MAX_OUTSTANDING_RD,
m_max_outstanding_read_trans, index, axi4_tr_if_0(index));
set_config(AXI4_CONFIG_MAX_OUTSTANDING_WR,
m_max_outstanding_write_trans, index, axi4_tr_if_0(index));
wait_on(AXI4_RESET_0_TO_1, index, axi4_tr_if_0(index));
wait_on(AXI4_CLOCK_POSEDGE, index, axi4_tr_if_0(index));
loop
create_slave_transaction(write_trans, index, axi4_tr_if_0(index));
get_write_addr_phase(write_trans, index, axi4_tr_if_0(index));
get_config(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE,
tmp_config_num_outstanding_wr_phase, index, axi4_tr_if_0(index));
push_transaction_id(write_trans, AXI4_QUEUE_ID_0, index,
axi4_tr_if_0(index));
end loop;
wait;
end process;
-- handle_write : write data phase through path 1
-- This method receive write data burst or phases for write transaction
-- depending upon slave working mode and write data to memory.
process
variable write_trans: integer;
variable byte_length : integer;
variable burst_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
variable last : integer := 0;
variable loop_i : integer := 0;
begin
loop
pop_transaction_id(write_trans, AXI4_QUEUE_ID_0, index, AXI4_PATH_1,
axi4_tr_if_1(index));
if (slave_mode = AXI4_TRANSACTION_SLAVE) then
get_write_data_burst(write_trans, index, AXI4_PATH_1,
axi4_tr_if_1(index));
get_burst_length(burst_length, write_trans, index, AXI4_PATH_1,
axi4_tr_if_1(index));
for i in 0 to burst_length loop
get_write_addr_data(write_trans, i, 0, byte_length, addr, data,
index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_write_addr_data(write_trans, i, j, byte_length, addr,
data, index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
end loop;
end if;
end loop;
else
last := 0;
loop_i := 0;
while(last = 0) loop
get_write_data_phase(write_trans, loop_i, last, index,
AXI4_PATH_1, axi4_tr_if_1(index));