Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 628)

Mentor VIP AE AXI3/4 User Guide, V10.2b 608
VHDL Tutorials
Verifying a Slave DUT
September 2013
A top-level file instantiates and connects all the components required to test and monitor the
DUT, and controls the system clock (ACLK) and reset (ARESETn) signals.
AXI3 BFM Master Test Program
Using the AXI3 master BFM API, this Master Test Program creates a wide range of stimulus
scenarios which test the slave DUT. This tutorial restricts the stimulus to a write transaction
followed by a read transaction to the same address, which then compares the read data with the
previously written data. For a complete code example of this VHDL Master Test Program, refer
to
“VHDL AXI3 Master BFM Test Program” on page 731 in Appendix B.
Configuration and Initialization
The code excerpt in Example 11-1 shows the Master Test Program architecture definition
master_test_program_a. It defines three variables, tr_id, data_words, and lp to hold the
transaction identifier number, data words payload, and read data from the slave, respectively.
An additional system clock cycle is waited on after reset to satisfy the AXI3 protocol
requirement specified in Section 11.1.2 of the AMBA AXI Protocol Specification before
executing transactions.
Example 11-1. Architecture Definition and Initialization
architecture master_test_program_a of master_test_program is
begin
-- Master test
process
variable tr_id: integer;
variable data_words : std_logic_vector(AXI_MAX_BIT_SIZE-1 downto 0);
variable lp: line;
begin
wait_on(AXI_RESET_0_TO_1, index, axi_tr_if_0(index));
wait_on(AXI_CLOCK_POSEDGE, index, axi_tr_if_0(index));
Write Transaction Creation and Execution
To generate AXI3 protocol traffic, the Master Test Program must create the transaction before
executing it. The code excerpt in
Example 11-2 uses the VHDL Master API
create_write_transaction() procedure, providing only the start address argument of the
transaction. The optional burst-length argument automatically defaults to a value of zero—
indicating a burst length of a single beat.
This example has an AXI3 data bus width of 32-bits; therefore a single beat of data conveys 4-
bytes across the data bus. The
set_data_words() procedure sets the data_words[0] transaction
field with the value of 1 on byte lane 1, resulting in a value of 32'h0000_0100. However, the
AXI3 protocol permits narrow transfers with the use of the write strobes signal WSTRB to
indicate which byte lane contains valid write data, and therefore indicates to the slave DUT