Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 647)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 627
September 2013
You can edit this procedure to change the RVALID signals delays.
Example 11-22. set_read_data_valid_delay()
-- Procedure : set_read_data_valid_delay
-- This will set the ready delays for each write data phase in a write data
-- burst
procedure set_read_data_valid_delay
(
id : integer; signal tr_if : inout axi_vhd_if_struct_t
) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, tr_if);
for i in 0 to burst_length loop
set_data_valid_delay(i, i, id, index, tr_if);
end loop;
end set_read_data_valid_delay;
procedure set_read_data_valid_delay
(
id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t
) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, path_id, tr_if);
for i in 0 to burst_length loop
set_data_valid_delay(i, i, id, index, path_id, tr_if);
end loop;
end set_read_data_valid_delay;
The set_wr_resp_valid_delay() procedure has two prototypes, one for multiple process threads
by providing the path_id argument. When called, it configures the BREADY signal handshake to
be delayed by a number of ACLK cycles, which extends the length of the write response phase.
The starting point of the delay is determined by the configuration of the delay_mode operational
transaction field (refer to
“AXI3 BFM Delay Mode” on page 30 for details). Example 11-23
demonstrates setting the BREADY signal delay by 2 ACLK cycles.