Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 82)

Mentor VIP AE AXI3/4 User Guide, V10.2b 64
SystemVerilog AXI3 and AXI4 Master BFMs
get_write_response_cycle()
September 2013
get_write_response_cycle()
This blocking AXI4 task waits until the write response channel BVALID signal is asserted.
AXI3 BFM
Note
The get_write_response_cycle() task is not available in the AXI3 BFM.
AXI4 Example
// Wait until the write response channel BVALID signal is asserted.
bfm.get_write_response_cycle();
Prototype task automatic get_write_response_cycle();
Arguments None
Returns None