Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 741)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 721
September 2013
} axi4_slave_mode_e;
// Enum type for slave ready delay mode
// AXI4_VALID2READY - Ready delay for a phase will be applied from
// start of phase (Means from when VALID is asserted).
// AXI4_TRANS2READY - Ready delay will be applied from the end of
// previous phase. This might result in ready before
// valid.
typedef enum bit
{
AXI4_VALID2READY = 1'b0,
AXI4_TRANS2READY = 1'b1
} axi4_slave_ready_delay_mode_e;
/////////////////////////////////////////////////
// Code user could edit according to requirements
/////////////////////////////////////////////////
// Slave max outstanding reads
int m_max_outstanding_read_trans = 2;
// Slave max outstanding writes
int m_max_outstanding_write_trans = 2;
// Variable : m_wr_addr_phase_ready_delay
int m_wr_addr_phase_ready_delay = 2;
// Variable : m_rd_addr_phase_ready_delay
int m_rd_addr_phase_ready_delay = 2;
// Variable : m_wr_data_phase_ready_delay
int m_wr_data_phase_ready_delay = 2;
// Slave ready delay mode seclection : default it is VALID2READY
axi4_slave_ready_delay_mode_e slave_ready_delay_mode = AXI4_VALID2READY;
// Slave mode seclection : default it is transaction level slave
axi4_slave_mode_e slave_mode = AXI4_TRANSACTION_SLAVE;
// Storage for a memory
bit [7:0] mem [*];
// Function : do_byte_read
// Function to provide read data byte from memory at particular input
// address
function bit[7:0] do_byte_read(addr_t addr);
return mem[addr];
endfunction
// Function : do_byte_write
// Function to write data byte to memory at particular input address
function void do_byte_write(addr_t addr, bit [7:0] data);
mem[addr] = data;
endfunction
// Function : set_wr_resp_valid_delay
// This is used to set write response phase valid delay to start driving
// write response phase after specified delay.