Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 52)

Mentor VIP AE AXI3/4 User Guide, V10.2b 34
SystemVerilog AXI3 and AXI4 Master BFMs
Master BFM Configuration
September 2013
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local or site-wide simulator initialization files.
If there is no timescale directive, the default time unit and time precision are tool specific. The
recommended practice is to use timeunit and timeprecision declarations. Refer to the
SystemVerilog LRM section 3.14 for details.
Master BFM Configuration
A master BFM supports the full range of signals defined for the AMBA AXI protocol
specification. It has parameters that configure the widths of the address, ID and data signals, and
transaction fields to specify timeout factors, slave exclusive support, setup and hold times, etc.
The address, ID and data signal widths can be changed from their default settings by assigning
them new values, usually in the top-level module of the testbench. These new values are then
passed to the master BFM using a parameter port list of the master BFM module. For example,
the code extract below shows the AXI3 master BFM with the address, ID and data signal widths
defined in module top() and passed to the master BFM mgc_axi_master parameter port list:
module top ();
parameter AXI_ADDRESS_WIDTH = 24;
parameter AXI_RDATA_WIDTH = 16;
parameter AXI_WDATA_WIDTH = 16;
parameter AXI_ID_WIDTH = 4;
mgc_axi_master #(AXI_ADDRESS_WIDTH, AXI_RDATA_WIDTH, AXI_WDATA_WIDTH,
AXI_ID_WIDTH) bfm_master(....);
Note
In the above code extract, the mgc_axi_master is the AXI3 master BFM interface.
The following table lists parameter names for the address, ID and data signals, and their default
values.
Table 3-1. Master BFM Signal Width Parameters
Signal Width Parameter
(Note: ** = AXI or AXI4)
Description
**_ADDRESS_WIDTH Address signal width in bits. This applies to the ARADDR and
AWADDR signals. Refer to the AMBA AXI Protocol
specification for more details. Default: 32.
**_RDATA_WIDTH Read data signal width in bits. This applies to the RDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.
**_WDATA_WIDTH Write data signal width in bits. This applies to the WDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.