Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 739)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 719
September 2013
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.RVALID === 1'b1) && (bfm.RREADY === 1'b1)));
end
fork
bfm.execute_read_data_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);
fork
bfm.execute_read_data_ready(1'b1);
join_none
seen_valid_ready = 1'b0;
end
end
endtask
endmodule