Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 769)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 749
September 2013
);
end slave_test_program;
architecture slave_test_program_a of slave_test_program is
type axi4_slave_mode_e is (AXI4_TRANSACTION_SLAVE, AXI4_PHASE_SLAVE);
type memory_t is array (0 to 2**16-1) of std_logic_vector(7 downto 0);
--///////////////////////////////////////////////
-- Code user could edit according to requirements
--///////////////////////////////////////////////
-- Variable : m_wr_addr_phase_ready_delay
signal m_wr_addr_phase_ready_delay : integer := 1;
-- Variable : m_rd_addr_phase_ready_delay
signal m_rd_addr_phase_ready_delay : integer := 1;
-- Variable : m_wr_data_phase_ready_delay
signal m_wr_data_phase_ready_delay : integer := 1;
-- Variable : m_max_outstanding_read_trans
signal m_max_outstanding_read_trans : integer := 2;
-- Variable : m_max_outstanding_write_trans
signal m_max_outstanding_write_trans : integer := 2;
-- Variable : tmp_config_num_outstanding_wr_phase
shared variable tmp_config_num_outstanding_wr_phase : integer;
-- Variable : tmp_config_num_outstanding_rd_phase
shared variable tmp_config_num_outstanding_rd_phase : integer;
-- Slave mode seclection : default it is transaction level slave
signal slave_mode : axi4_slave_mode_e := AXI4_TRANSACTION_SLAVE;
-- Storage for a memory
shared variable mem : memory_t;
procedure do_byte_read(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0));
procedure do_byte_write(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0));
procedure set_wr_resp_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t);
procedure set_wr_resp_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t);
procedure set_read_data_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t);
-- Procedure : do_byte_read
-- Procedure to provide read data byte from memory at particular input
-- address
procedure do_byte_read(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : out std_logic_vector(7 downto 0)) is
begin
data := mem(to_integer(addr));