Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 678)

Mentor VIP AE AXI3/4 User Guide, V10.2b 658
Getting Started with Qsys and the BFMs
Setting Up Simulation from the Windows GUI
September 2013
6. Change the example’s path, select the simulation model, and turn off synthesis as
outlined in the steps below and shown in Figure 12-7 .
Figure 12-7. Set Path, Simulation and Synthesis Options
a. Change the example’s path. In the Path field of the Output Directory section, ensure
the path correctly specifies the subdirectory ex1_back_to_back_sv, which is the
subdirectory containing the example that you just copied into a temporary directory.
Note
If the subdirectory name of the example is duplicated in the example’s Path field, you
must remove one of the duplicated subdirectory names. To reset the path, double-click
the square browse button to the right of the Path field and locate the path of the example.
The example’s path specified by the Path field of the Output Directory section must
be correct before selecting Verilog or VHDL in the next step.
b. Under the Simulation section, select the language for your output files, Verilog or
VHDL, for the value of the Create simulation model option (refer to Figure 12-7 ).
c. Under the Testbench System section, set the Create testbench Qsys system to None,
along with the Create testbench simulation model option (refer to Figure 12-7 ).
d. Under the Synthesis section, set the Create HDL design files for synthesis to None,
and be sure the Create block symbol file is unchecked (refer to Figure 12-7 ).
e. Click the Generate button on the bottom left side of the window (refer to
Figure 12-8 ).