Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 481)

VHDL AXI3 and AXI4 Slave BFMs
get_write_addr_cycle()
Mentor VIP AE AXI3/4 User Guide, V10.2b 461
September 2013
get_write_addr_cycle()
This blocking AXI4 procedure waits until the write address channel AWVALID signal is
asserted.
AXI3 BFM
Note
The get_write_addr_cycle() procedure is not available in the AXI3 BFM.
AXI4 Example
// Wait for the AWVALID signal to be asserted.
bfm.get_write_addr_cycle(bfm_index, axi4_tr_if_0(bfm_index));
Prototype procedure get_write_addr_cycle
(
bfm_id : in integer;
path_id : in axi4_adv_path_t; --optional
signal tr_if : inout axi4_vhd_if_struct_t
);
Arguments bfm_id BFM identifier. Refer to “Overloaded Procedure Common Arguments”
on page 203 for more details.
path_id (Optional) Parallel process path identifier:
AXI4_PATH_5
AXI4_PATH_6
AXI4_PATH_7
Refer to “Overloaded Procedure Common Arguments” on page 203 for
more details.
tr_if Transaction signal interface. Refer to “Overloaded Procedure Common
Arguments” on page 203 for more details.
Returns None