Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 645)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 625
September 2013
The set_write_address_ready_delay() procedure has two prototypes, one for multiple process
threads by providing the path_id argument. When called it configures the AWREADY
handshake signal to be delayed by a number of ACLK cycles, which extends the length of the
write address phase. The starting point of the delay is determined by the configuration of the
delay_mode operational transaction field (refer to
“AXI3 BFM Delay Mode” on page 30 for
details). Example 11-20 demonstrates setting the AWREADY signal delay by 2 ACLK cycles.
You can edit this procedure to change the AWREADY signal delay.
Example 11-20. set_write_address_ready_delay()
-- Procedure : set_write_address_ready_delay
-- This is used to set write address phase ready delay to extend phase
procedure set_write_address_ready_delay
(
id : integer; signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_address_ready_delay(2, id, index, tr_if);
end set_write_address_ready_delay;
procedure set_write_address_ready_delay
(
id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_address_ready_delay(2, id, index, path_id, tr_if);
end set_write_address_ready_delay;
The set_write_data_ready_delay() procedure has two prototypes, one for multiple process
threads by providing the path_id argument. When called it configures the WREADY signal
handshake to be delayed by a number of ACLK cycles which extends the length of each write
data phase (beat) in a write data burst. The starting point of the delay is determined by the
configuration of the delay_mode operational transaction field (refer to
“AXI3 BFM Delay
Mode” on page 30 for details).
For each write data phase (beat) the delay value of the WREADY signal is stored in an element
of the data_ready_delay[] array for the transaction, as demonstrated in
Example 11-21 .