Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 670)

Mentor VIP AE AXI3/4 User Guide, V10.2b 650
VHDL Tutorials
Verifying a Master DUT
September 2013
else
last := 0;
loop_i := 0;
while(last = 0) loop
get_write_data_phase(write_trans, loop_i, last, index,
AXI4_PATH_1, axi4_tr_if_1(index));
get_write_addr_data(write_trans, loop_i, 0, byte_length,
addr, data, index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_write_addr_data(write_trans, loop_i, j,
byte_length, addr, data, index, AXI4_PATH_1, axi4_tr_if_1(index));
do_byte_write(addr, data);
end loop;
end if;
loop_i := loop_i + 1;
end loop;
end if;
push_transaction_id(write_trans, AXI4_QUEUE_ID_2, index,
AXI4_PATH_1, axi4_tr_if_1(index));
end loop;
wait;
end process;