Monitor bfm protocol support, Monitor timing and events, Monitor bfm configuration – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
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Mentor VIP AE AXI3/4 User Guide, V10.2b
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SystemVerilog AXI3 and AXI4 Monitor BFMs
Monitor BFM Protocol Support
September 2013
Monitor BFM Protocol Support
The AXI3 monitor BFM supports the AMBA AXI3 protocol with restrictions described in
on page 1. In addition to the standard protocol, it supports user sideband
signals AWUSER and ARUSER.
The AXI4 monitor BFM supports the AMBA AXI4 protocol with restrictions described in
Monitor Timing and Events
For detailed timing diagrams of the protocol bus activity refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following monitor
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the monitor BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the
testbench and design IP as a result of:
•
timescale directives in design elements.
•
timeprecision declarations in design elements.
•
compiler command-line options.
•
simulation command-line options.
•
local or site-wide simulator initialization files.
If there is no timescale directive, the default time unit and time precision are tool specific.The
recommended practice is to use timeunit and timeprecision declarations. Refer to the
SystemVerilog LRM section 3.14 for details.
Monitor BFM Configuration
The monitor BFM supports the full range of signals defined for the AMBA AXI protocol
specification. It has parameters you can use to configure the widths of the address, ID and data
signals, and transaction fields to configure timeout factors, slave exclusive support, setup and
hold times, etc.
You can change the address, ID and data signals widths from their default settings by assigning
them with new values, usually performed in the top-level module of the testbench. These new
values are then passed into the monitor BFM via a parameter port list of the monitor BFM