Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 725)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI3 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 705
September 2013
// Function : set_write_data_ready_delay
// This will set the ready delays for each write data phase in a write
data
// burst
function void set_write_data_ready_delay(axi_transaction trans);
for (int i = 0; i < trans.data_ready_delay.size(); i++)
trans.set_data_ready_delay(i, i);
endfunction
// Function : set_wr_resp_valid_delay
// This is used to set write response phase valid delay to start driving
// write response phase after specified delay.
function void set_wr_resp_valid_delay(axi_transaction trans);
trans.set_write_response_valid_delay(2);
endfunction
// Function : set_read_data_valid_delay
// This is used to set read response phase valid delays to start driving
// read data/response phases after specified delay.
function void set_read_data_valid_delay(axi_transaction trans);
for (int i = 0; i < trans.data_valid_delay.size(); i++)
trans.set_data_valid_delay(i, 10);
endfunction
///////////////////////////////////////////////////////////////////////
// Code user do not need to edit
// Please note that in this part of code base below delays are assigned
// which user might need to change according to requirement
// address_ready_delay : This is for write and read address phase both
// data_valid_delay : This is for sending read data/response valid
// data_ready_delay : This is for write data phase ready delay
///////////////////////////////////////////////////////////////////////
initial
begin
// Initialisation
bfm.set_config(AXI_CONFIG_MAX_OUTSTANDING_RD,m_max_outstanding_read_trans
);
bfm.set_config(AXI_CONFIG_MAX_OUTSTANDING_WR,m_max_outstanding_write_tran
s);
bfm.wait_on(AXI_RESET_0_TO_1);
bfm.wait_on(AXI_CLOCK_POSEDGE);
// Traffic generation
fork
process_read;
process_write;
join
end