Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 734)

Mentor VIP AE AXI3/4 User Guide, V10.2b 714
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
September 2013
$display ( "@ %t, master_test_program: Error: Expected data
(hACE2ACE3) at address (132), but got %h", $time,
trans.get_data_words(1));
/************************************
** Outstanding Traffic generation: **
************************************/
repeat(10)
bfm.wait_on(AXI4_CLOCK_POSEDGE);
// 4 x Writes
// Write data value to address 0.
trans1 = bfm.create_write_transaction(0,3);
trans1.set_data_words('hACE0ACE1, 0);
trans1.set_data_words('hACE2ACE3, 1);
trans1.set_data_words('hACE4ACE5, 2);
trans1.set_data_words('hACE6ACE7, 3);
for(int i=0; i<4; i++)
trans1.set_write_strobes(4'b1111, i);
$display ( "@ %t, master_test_program: Writing data (1) to address
(0)", $time);
fork
bfm.execute_write_addr_phase(trans1);
bfm.execute_write_data_burst(trans1);
join_any
// Write data value to address 16.
trans2 = bfm.create_write_transaction(16,2);
trans2.set_data_words('hACE0ACE1, 0);
trans2.set_data_words('hACE2ACE3, 1);
trans2.set_data_words('hACE4ACE5, 2);
for(int i=0; i<3; i++)
trans2.set_write_strobes(4'b1111, i);
$display ( "@ %t, master_test_program: Writing data (2) to address
(16)", $time);
fork
bfm.execute_write_addr_phase(trans2);
bfm.execute_write_data_burst(trans2);
join_any
// Write data value to address 32.
trans3 = bfm.create_write_transaction(32,4);
trans3.set_data_words('hACE0ACE1, 0);
trans3.set_data_words('hACE2ACE3, 1);
trans3.set_data_words('hACE4ACE5, 2);
trans3.set_data_words('hACE6ACE7, 3);
trans3.set_data_words('hACE8ACE9, 4);
for(int i=0; i<5; i++)
trans3.set_write_strobes(4'b1111, i);
$display ( "@ %t, master_test_program: Writing data (3) to address
(32)", $time);