Figure 7-1. vhdl bfm internal structure, Test program vhdl, Vhdl to sv wrapper – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual

Page 204: Translator package

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Mentor VIP AE AXI3/4 User Guide, V10.2b

186

VHDL API Overview

September 2013

Figure 7-1. VHDL BFM Internal Structure

Test Program VHDL

SV BFM API

Configuration

Creating
Transaction

Waiting Events

Executing
Transaction

Access
Transaction

create*_transaction

1

set_config/get_config

execute_transaction/execute*_burst/execute*_phase

2

wait_on
get*_burst/get*_phase

3

get_rw_transaction/get*_burst/get*_phase

3

get*_addr/get*_data

3

Wire Level

SV Interface

Notes: 1. Refer to the

create*_transaction()

2. Refer to the

execute_transaction(), execute*_burst(), execute*_phase()

3. Refer to the

get*()

Port Map

SV to VHDL

Rx_Transaction

queue

queue

Tx_Transaction

Configuration

Maps API calls from VHDL to SV

Translator Package

VHDL to SV Wrapper

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