Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 173)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 155
September 2013
handle_read_data_ready()
The handle_read_data_ready() task handles the RREADY signal for the read data channel. It
delays the assertion of the RREADY signal based on the settings of the
master_ready_delay_mode and m_rd_data_phase_ready_delay . The
handle_read_data_ready() task code is similar in operation to the handle_write_resp_ready()
task. Refer to the “SystemVerilog AXI4 Master BFM Test Program” on page 709 for the
complete handle_read_data_ready() code listing.
Verifying a Master DUT
A master DUT component is connected to a slave BFM at the signal-level. A slave test program,
written at the transaction-level, generates stimulus via the slave BFM to verify the master DUT.
Figure 6-4 illustrates a typical top-level testbench environment.
Figure 6-4. Master DUT Top-level Testbench Environment
In this example the slave test program is a simple memory model.
A top-level file instantiates and connects all the components required to test and monitor the
DUT, and controls the system clock (ACLK) and reset (ARESETn) signals.
AXI3 BFM Slave Test Program
The slave test program is a memory model and contains two APIs: a AXI3 Basic Slave API
Definition and an Advanced AXI3 Slave API Definition .
The AXI3 Basic Slave API Definition allows you to create a wide range of stimulus scenarios to
test a master DUT. This API definition simplifies the creation of slave stimulus based on the
default response of OKAY to read and write transactions.
Program
Test
Slave
BFM Master
DUT
Slave
Top-level File