Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 729)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 709
September 2013
SystemVerilog AXI4 Master BFM Test Program
The following code example contains a simple AXI4 master test program that shows the master
BFM API being used to communicate with a slave and create stimulus. This test program is
discussed further in the
SystemVerilog Tutorials chapter.
// **********************************************************************
//
// Copyright 2007-2013 Mentor Graphics Corporation
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
// THE PROPERTY OF
// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
// TERMS.
//
// **********************************************************************
/*
This is a simple example of an AXI4 master to demonstrate the
mgc_axi4_master BFM usage.
This master performs a directed test, initiating 4 sequential writes,
followed by 4 sequential reads. It then verifies that the data read out
matches the data written.
For the sake of simplicity, only one data cycle is used (default AXI4
burst length encoding 0).
It then initiates two write data bursts followed by two read data
bursts.
It then initiates 4 outstanding writes, followed by 4 reads. It then
verifies that the data read out matches the data written.
*/
import mgc_axi4_pkg::*;
module master_test_program #(int AXI4_ADDRESS_WIDTH = 32, int
AXI4_RDATA_WIDTH = 1024, int AXI4_WDATA_WIDTH = 1024, int AXI4_ID_WIDTH =
18, int AXI4_USER_WIDTH = 8, int AXI4_REGION_MAP_SIZE = 16)
(
mgc_axi4_master bfm
);