Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 201)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 183
September 2013
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_addr_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.AWVALID === 1'b1) && (bfm.AWREADY === 1'b1)));
end
fork
bfm.execute_write_addr_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);
fork
bfm.execute_write_addr_ready(1'b1);
join_none
seen_valid_ready = 1'b0;
end
end
endtask
Example 6-47.
handle_read_addr_ready()
The handle_read_addr_ready() task handles the ARREADY signal for the read address channel.
In a forever loop, it delays the assertion of the ARREADY signal based on the settings of the
slave_ready_delay_mode and m_rd_addr_phase_ready_delay . The handle_read_addr_ready()
task code is similar in operation to the handle_write_addr_ready() task. Refer to the
“SystemVerilog AXI4 Slave BFM Test Program” on page 720 for the complete
handle_read_addr_ready() code listing.
handle_write_data_ready()
The handle_write_data_ready() task handles the WREADY signal for the write data channel. In
a forever loop it delays the assertion of the WREADY signal based on the settings of the
slave_ready_delay_mode and m_wr_data_phase_ready_delay . The handle_write_data_ready()
task code is similar in operation to the handle_write_addr_ready() task. Refer to the
“SystemVerilog AXI4 Slave BFM Test Program” on page 720 for the complete
handle_write_data_ready() code listing.