Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 207)

VHDL API Overview
Creating Transactions
Mentor VIP AE AXI3/4 User Guide, V10.2b 189
September 2013
Example 7-1. AXI3 Transaction Definition
// Global Transaction Class
class axi_transaction;
// Protocol
bit [((`MAX_AXI_ADDRESS_WIDTH) - 1):0] addr;
axi_size_e size;
axi_burst_e burst;
axi_lock_e lock;
axi_cache_e cache;
axi_prot_e prot;
bit [((`MAX_AXI_ID_WIDTH) - 1):0] id;
bit [3:0] burst_length;
bit [((((`MAX_AXI_RDATA_WIDTH > `MAX_AXI_WDATA_WIDTH) ?
`MAX_AXI_RDATA_WIDTH : `MAX_AXI_WDATA_WIDTH)) - 1):0] data_words [];
bit [(((`MAX_AXI_WDATA_WIDTH / 8)) - 1):0] write_strobes [];
axi_response_e resp[];
bit [7:0] addr_user;
axi_rw_e read_or_write;
int address_valid_delay;
int data_valid_delay[];
int write_response_valid_delay;
int address_ready_delay;
int data_ready_delay[];
int write_response_ready_delay;
// Housekeeping
bit gen_write_strobes = 1'b1;
axi_operation_mode_e operation_mode = AXI_TRANSACTION_BLOCKING;
axi_delay_mode_e delay_mode = AXI_VALID2READY;
axi_write_data_mode_e write_data_mode = AXI_DATA_AFTER_ADDRESS;
bit data_beat_done[];
bit transaction_done;
...
endclass
Note
The axi_transaction class code above is shown for information only. Access to each
transaction record during its lifetime is performed via the various set*() and get*()
procedures detailed later in this Chapter.
AXI4 Transaction Definition
The transaction record exists as a SystemVerilog class definition in each BFM. Example 7-2
below shows the definition of the axi4_transaction class members that form the transaction
record.