Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 633)

VHDL Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 613
September 2013
The call to the set_write_data_mode() procedure configures the address phase to occur before
the start of the data burst when the transaction is executed by setting the write_data_mode to be
AXI_DATA_AFTER_ADDRESS. The call to the
set_operation_mode() procedure configures the
transaction to be nonblocking by setting the operation_mode field to
AXI_TRANSACTION_NON_BLOCKING.
The write transaction is then executed onto the protocol signals by calling the
execute_transaction() procedure. The executed transaction will be nonblocking allowing
subsequent address phase transactions to be executed before the current write data burst has
completed. This allows outstanding write transaction stimulus to be created.
Example 11-6. Outstanding Write Burst Transaction Creation and Execution
create_write_transaction(0, 3, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE0ACE1";
set_data_words(data_words, 0, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE2ACE3";
set_data_words(data_words, 1, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE4ACE5";
set_data_words(data_words, 2, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE6ACE7";
set_data_words(data_words, 3, tr_id, index, axi_tr_if_0(index));
for i in 0 to 3 loop
set_write_strobes(15, i, tr_id, index, axi_tr_if_0(index));
end loop;
set_write_data_mode(AXI_DATA_AFTER_ADDRESS, tr_id, index,
axi_tr_if_0(index));
set_operation_mode(AXI_TRANSACTION_NON_BLOCKING, tr_id, index,
axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
Subsequent write transaction are created and executed in a similar manner to that shown in
Example 11-2 . See VHDL AXI3 Slave BFM Test Program listing for details.
AXI4 BFM Master Test Program
A master test program using the master BFM API is capable of creating a wide range of
stimulus scenarios to verify a slave DUT. However, this tutorial restricts the master BFM
stimulus to write transactions followed by read transactions to the same address, and then
compares the read data with the previously written data. For a complete code listing of this
master test program, refer to
“VHDL AXI4 Master BFM Test Program” on page 743.
The master test program contains:
•
A create_transactions process that creates and executes read and write transactions.
•
Processes handle_write_resp_ready and handle_read_data_ready to handle the write
response channel BREADY and read data channel RREADY signals, respectively.