Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 161)

SystemVerilog Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 143
September 2013
The write transaction trans1 is then executed onto the protocol signals by calling the
execute_write_addr_phase() and execute_write_data_burst() functions in parallel within a
fork.. join_any statement. By calling the execute_write_addr_phase() and
execute_write_data_burst() functions in parallel, subsequent address phase transactions can be
executed before the current write data burst has completed. This allows outstanding write
transaction stimulus to be created.
Example 6-6. Outstanding Write Burst Transaction Creation and Execution
/************************
** Traffic generation: **
************************/
// 4 x Writes
// Write data value to address 1.
trans1 = bfm.create_write_transaction(1,3); //Burst length=3+1
trans1.set_data_words('hACE0ACE1, 0);
trans1.set_data_words('hACE2ACE3, 1);
trans1.set_data_words('hACE4ACE5, 2);
trans1.set_data_words('hACE6ACE7, 3);
for(int i=0; i<4; i++)
trans1.set_write_strobes(4'b1111, i);
$display ( "@ %t, master_test_program: Writing data (1) to address (1)",
$time);
// By default it will run in Blocking mode
fork
bfm.execute_write_addr_phase(trans1);
bfm.execute_write_data_burst(trans1);
join_any
Subsequent write transaction are created and assigned to unique variables, trans2, trans3,
trans4, etc, allowing multiple write transactions to exist at the same time. The write transactions
are then executed in a similar manner to that shown in
Example 6-6 , resulting in outstanding
write transactions. See the SystemVerilog AXI3 Master BFM Test Program code listing for
details.
AXI4 BFM Master Test Program
A master test program using the master BFM API is capable of creating a wide range of
stimulus scenarios to verify a slave DUT. However, this tutorial restricts the master BFM
stimulus to write transactions followed by read transactions to the same address, and then
compares the read data with the previously written data. For a complete code listing of this
master test program, refer to
“SystemVerilog AXI4 Master BFM Test Program” on page 709 .
The master test program contains:
•
A Configuration and Initialization that creates and executes read and write transactions.