Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 743)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 723
September 2013
///////////////////////////////////////////////////////////////////////
// Code user do not need to edit
// Note that in this part of code base below, valid delays are assigned
// which the user might need to change according to requirements
// data_valid_delay : This is for sending read data/response valid
///////////////////////////////////////////////////////////////////////
initial
begin
// Initialization
bfm.set_config(AXI4_CONFIG_MAX_OUTSTANDING_RD,m_max_outstanding_read_tran
s);
bfm.set_config(AXI4_CONFIG_MAX_OUTSTANDING_WR,m_max_outstanding_write_tra
ns);
bfm.wait_on(AXI4_RESET_0_TO_1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
// Traffic generation
fork
process_read;
process_write;
handle_write_addr_ready;
handle_read_addr_ready;
handle_write_data_ready;
join
end
// Task : process_read
// This method keep receiving read address phase and calls another
// method to
// process received transaction.
task process_read;
forever
begin
axi4_transaction read_trans;
read_trans = bfm.create_slave_transaction();
bfm.get_read_addr_phase(read_trans);
fork
begin
automatic axi4_transaction t = read_trans;
handle_read(t);
end
join_none
#0;
end
endtask
// Task : handle_read
// This method reads data from memory and send read data/response
// either at