Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 667)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 647
September 2013
tmp_config_num_outstanding_rd_phase :=
tmp_config_num_outstanding_rd_phase - 1;
end loop;
wait;
end process;