Chapter 9 vhdl axi3 and axi4 slave bfms, Slave bfm protocol support, Slave timing and events – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual

Page 365: Slave bfm configuration

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Mentor VIP AE AXI3/4 User Guide, V10.2b

345

September 2013

Chapter 9

VHDL AXI3 and AXI4 Slave BFMs

This chapter provides information about the VHDL AXI3 and AXI4 slave BFMs. Each BFM
has an API that contains procedures to configure the BFM and to access the

Transaction Record

during the lifetime of the transaction.

Note

Due to AXI3 protocol specification changes, for some BFM tasks, you reference the
AXI3 BFM by specifying AXI instead of AXI3.

Slave BFM Protocol Support

The AXI3 Slave BFM implements the AMBA

AXI3 protocol with restrictions detailed in

“Protocol Restrictions”

on page 1. In addition to the standard protocol, it supports user sideband

signals AWUSER and ARUSER.

The AXI4 slave BFM supports the AMBA AXI4 protocol with restrictions detailed in

“Protocol

Restrictions”

on page 1.

Slave Timing and Events

For detailed timing diagrams of the protocol bus activity refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following slave
BFM API timing and events.

The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.

Slave BFM Configuration

The slave BFM supports the full range of signals defined for the AMBA AXI protocol
specification. The BFM has parameters that can be used to configure the widths of the address,
ID and data signals and transaction fields to configure timeout factors, slave exclusive support,
setup and hold times, etc.

The address, ID and data signals widths can be changed from their default settings by assigning
them with new values, usually performed in the top-level module of the testbench. These new

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